System level EDA tools allow a designer to model, simulate, and analyze systems. Tools such as Simulink® from MathWorks® allow designers to create, simulate, evaluate, and refine a system design model through standard and custom block libraries. When designing a system with a system level EDA tool, it is desirable to have the capability to inspect various nodes of the model using visual waveform display. Among others, this facilitates the analysis of signal synchronization as well as signal dynamic range and could therefore drastically reduce the debug phase.
Existing system level EDA tools which do not read register transfer level (RTL) (VHDL or Verilog) model support very limited waveform viewing capabilities and do not always provide a user-friendly way method for designers to analyze signal synchronization. Designers interested in performing a more detailed waveform analysis were required to use techniques outside system level EDA tools. One of the techniques used for generating a more detailed waveform of data signals from a system design model included converting an entire system design model into a RTL representation. This involved converting the system design model into a hardware design language such as Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) or Verilog and simulating the entire system design model in an RTL simulator. This is for instance the flow used by tools such as DSP Builder. This approach required a significant amount of additional time and computing resources that resulted in slowing the design cycle which was undesirable. In addition, this approach failed to work on non RTL synthesizable system design models.
Thus, what is needed is an efficient method and apparatus for enabling waveform display on an EDA tool.